US 12,373,350 B2
Cache-line retention hint information for conditional write instruction
Matthew James Horsnell, Cambridge (GB); Andreas Lars Sandberg, Cambridge (GB); Thomas Philip Speier, Wake Forest, NC (US); Robin Alexander Emery, Cambridge (GB); and Eric Ola Harald Liljedahl, Stockholm (SE)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 22, 2023, as Appl. No. 18/394,400.
Prior Publication US 2025/0209007 A1, Jun. 26, 2025
Int. Cl. G06F 12/0875 (2016.01); G06F 9/30 (2018.01)
CPC G06F 12/0875 (2013.01) [G06F 9/3016 (2013.01); G06F 2212/452 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
instruction decoding circuitry to decode a sequence of instructions; and
processing circuitry to perform data processing in response to decoding of the sequence of instructions by the instruction decoding circuitry; in which:
in response to the instruction decoding circuitry decoding a conditional write instruction, the processing circuitry is configured to:
determine whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction;
in response to determining that the predetermined condition is satisfied for the target cache line, issue a write request to update the target cache line; and
in response to determining that the predetermined condition is not satisfied for the target cache line, return a failure indication; and
select, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction, the unique coherency state comprising a coherency state in which the processing circuitry has exclusive right to update the target cache line.