US 12,372,571 B2
Method and device for detecting layout of integrated circuit, and storage medium
Miaomiao Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 8, 2022, as Appl. No. 17/806,072.
Application 17/806,072 is a continuation of application No. PCT/CN2021/138423, filed on Dec. 15, 2021.
Claims priority of application No. 202111293505.8 (CN), filed on Nov. 3, 2021.
Prior Publication US 2023/0133766 A1, May 4, 2023
Int. Cl. G01R 31/26 (2020.01); G06F 30/392 (2020.01)
CPC G01R 31/2621 (2013.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for detecting a layout of an integrated circuit, comprising:
determining a finger structure in the layout, wherein the finger structure comprises at least one upper connected source-drain terminal and at least one upper connected via, and the at least one upper connected source-drain terminal is electrically connected to an upper metal line through the at least one upper connected via;
calculating a number of the at least one upper connected source-drain terminal and a number of the at least one upper connected via; and
for the finger structure, in response to the number of the at least one upper connected source-drain terminal being greater than the number of the at least one upper connected via, determining that the finger structure is an unqualified finger structure.