CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] | 18 Claims |
1. A non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to:
perform an erase process for the plurality of non-volatile memory cells,
detect that a subset of the plurality of non-volatile memory cells are slow to erase in response to the erase process, and
prevent successful programming for at least some of the non-volatile memory cells that are slow to erase.
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