US 12,046,294 B2
Non-volatile memory with short prevention
Yihang Liu, Santa Clara, CA (US); Xiaochen Zhu, Milpitas, CA (US); Lito De La Rama, San Jose, CA (US); and Feng Gao, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 23, 2022, as Appl. No. 17/847,553.
Prior Publication US 2023/0420055 A1, Dec. 28, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to:
perform an erase process for the plurality of non-volatile memory cells,
detect that a subset of the plurality of non-volatile memory cells are slow to erase in response to the erase process, and
prevent successful programming for at least some of the non-volatile memory cells that are slow to erase.