US 12,369,399 B2
Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure
Willy Rachmady, Beaverton, OR (US); Sudipto Naskar, Portland, OR (US); Cheng-Ying Huang, Hillsboro, OR (US); Gilbert Dewey, Beaverton, OR (US); Marko Radosavljevic, Portland, OR (US); Nicole K. Thomas, Portland, OR (US); Patrick Morrow, Portland, OR (US); and Urusa Alaan, Hillsboro, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/445,856.
Prior Publication US 2023/0073078 A1, Mar. 9, 2023
Int. Cl. H10D 30/62 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 86/60 (2025.01) [H10D 86/0221 (2025.01); H10D 86/451 (2025.01); H10D 86/421 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first semiconductor body;
a second semiconductor body above the first semiconductor body, wherein a longest distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 50 nm or less, and wherein the first and second semiconductor bodies are part of a same fin structure;
a first gate structure on the first semiconductor body such that a portion of the first gate structure contacts a top surface of the first semiconductor body;
a second gate structure on the second semiconductor body such that a portion of the second gate structure contacts a bottom surface of the second semiconductor body; and
an isolation structure between the portion of the first gate structure and the portion of the second gate structure and comprising dielectric material, wherein the isolation structure contacts and is conformal to a top surface of the portion of the first gate structure, and the isolation structure contacts a bottom surface of the portion of the second gate structure, wherein variation of the isolation structure thickness between the first and second gate structures is less than 1 nm.
 
11. An integrated circuit structure, comprising:
a first nanoribbon comprising a first semiconductor material;
a second nanoribbon above the first nanoribbon and comprising the first semiconductor material, wherein a distance between a top surface of the first nanoribbon and a bottom surface of the second nanoribbon is in the range of 15 to 50 nm, and wherein the first and second nanoribbons are part of a same multilayer fin structure;
a first gate structure around the first nanoribbon, the first gate structure including a first gate electrode and a first high-k gate dielectric between the first gate electrode and the first nanoribbon;
a second gate structure around the second nanoribbon, the second gate structure including a second gate electrode and a second high-k gate dielectric between the second gate electrode and the second nanoribbon; and
an isolation structure between the first and second nanoribbons and between the first and second gate structures and comprising dielectric material, wherein the isolation structure contacts and is conformal to a top surface of the first gate structure, and the isolation structure contacts a bottom surface of the second gate structure, wherein a largest thickness of the isolation structure between the first and second gate structures is within 10 angstroms of a smallest thickness of the isolation structure between the first and second gate structures.
 
18. An integrated circuit structure, comprising:
a first semiconductor body extending in a first direction from a first source or drain region;
a second semiconductor body above the first semiconductor body and extending in the first direction from a second source or drain region, wherein a longest distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 50 nm or less, and wherein the second source or drain region is above the first source or drain region;
a first gate structure on the first semiconductor body and extending in a second direction, such that a portion of the first gate structure contacts a top surface of the first semiconductor body;
a second gate structure on the second semiconductor body and extending in the second direction, such that a portion of the second gate structure contacts a bottom surface of the second semiconductor body; and
an isolation structure between the portion of the first gate structure and the portion of the second gate structure and comprising dielectric material, wherein the isolation structure abuts a top surface of the portion of the first gate structure and abuts a bottom surface of the portion of the second gate structure, and wherein variation of the isolation structure thickness between the first and second gate structures is less than 1 nm.