| CPC H10B 63/80 (2023.02) [H10N 70/063 (2023.02)] | 16 Claims |
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1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region;
a plurality of first lines disposed over the substrate and each extending in a first direction;
a plurality of second lines disposed over the first lines and each extending in a second direction crossing the first direction;
a plurality of memory cells positioned at intersections between the first lines and the second lines in the cell region;
a first insulating layer positioned between the plurality of first lines and the plurality of second lines, in the first cell region; and
a second insulating layer positioned between the plurality of first lines and the plurality of second lines, in the second cell region,
wherein a dielectric constant of the first insulating layer is smaller than a dielectric constant of the second insulating layer, and
wherein only one of the first insulating layer and the second insulating layer is filled between the memory cells.
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