US 12,369,320 B2
Vertical semiconductor device and method for fabricating the same
Wan Sup Shin, Gyeonggi-do (KR); Jong Gi Kim, Gyeonggi-do (KR); Seung Wook Ryu, Gyeonggi-do (KR); Jun Seok Oh, Gyeonggi-do (KR); and Heung Ju Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 15, 2022, as Appl. No. 17/671,888.
Claims priority of application No. 10-2021-0104829 (KR), filed on Aug. 9, 2021.
Prior Publication US 2023/0040214 A1, Feb. 9, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method for fabricating a vertical semiconductor device, comprising:
forming a lower-level stack including a source sacrificial layer over a semiconductor substrate;
forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack;
forming a vertical channel structure including a channel layer and a memory layer that penetrates the upper-level stack and the lower-level stack;
forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer;
forming a lateral recess that extends from the slit by removing the source sacrificial layer, wherein the forming the lateral recess forms vertically-extending undercuts in the memory layer, at least one of the vertically-extending undercuts extending into the source sacrificial layer over the semiconductor substrate;
forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess and while filling the vertically-extending undercuts;
selectively forming a second contact layer over an exposed surface of the first contact layer; and
selectively forming a chemical barrier layer over the second contact layer.