| CPC H10B 12/482 (2023.02) [H01L 21/0332 (2013.01); H01L 21/32139 (2013.01); H10B 12/0335 (2023.02); H10B 12/315 (2023.02); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10B 12/485 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a device isolation layer defining an active region in a substrate;
a word line buried in the substrate and crossing the active region;
a bit line crossing the word line on the substrate;
a spacer covering a sidewall of the bit line;
a mask pattern on the bit line, the mask pattern comprises:
a first mask pattern including a sidewall covered with the spacer; and
a second mask pattern on a top surface of the first mask pattern,
wherein the spacer exposes a sidewall of the second mask pattern,
wherein a top surface of the second mask pattern is higher than the top surface of the spacer, and
wherein the first mask pattern has a first line shape and the second mask pattern has a second line shape, the first line shape and the second line shape being aligned with the bit line in a plan view respectively.
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