US 12,369,301 B2
Memory device with semiconductor elements
Masakazu Kakumu, Tokyo (JP); Koji Sakui, Tokyo (JP); and Nozomu Harada, Tokyo (JP)
Assigned to UNISANTIS ELECTRONICS SINGAPORE PTE. LTD., Singapore (SG)
Filed by Unisantis Electronics Singapore Pte. Ltd., Singapore (SG)
Filed on Aug. 21, 2023, as Appl. No. 18/453,103.
Claims priority of application No. PCT/JP2022/031700 (WO), filed on Aug. 23, 2022.
Prior Publication US 2024/0074140 A1, Feb. 29, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 11/404 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4096 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory device with semiconductor elements, comprising:
a semiconductor base material extending on a substrate in a horizontal direction or a vertical direction;
a first impurity layer and a second impurity layer that are continuous with respective opposite ends of the semiconductor base material;
a first gate insulating layer partially covering the semiconductor base material;
a first gate conductor layer covering the first gate insulating layer;
a second gate insulating layer partially covering the semiconductor base material; and
a second gate conductor layer not in contact with the first gate conductor layer, the second gate conductor layer covering the second gate insulating layer,
wherein a memory write operation is performed by first applying a first voltage to allow a potential difference to be generated between the first impurity layer and the second impurity layer, and then applying second and third voltages each having the same polarity as a polarity of the first voltage to the first gate conductor layer and the second conductor layer, respectively, thereby increasing majority carriers in the semiconductor base material through an impact ionization phenomenon,
a memory erase operation is performed by first applying a fourth voltage to one of the first gate conductor layer and the second gate conductor layer, and then applying a fifth voltage having the same polarity as a polarity of the fourth voltage to allow a potential difference to be generated between the first impurity layer and the second impurity layer, thereby reducing majority carriers remaining in the semiconductor base material, and
a memory read operation is performed by first applying a sixth voltage to allow a potential difference to be generated between the first impurity layer and the second impurity layer, and then applying a seventh voltage to one of the first gate conductor layer and the second gate conductor layer, and thereafter applying an eighth voltage having the same polarity as a polarity of the seventh voltage to another of the first gate conductor layer and the second gate conductor layer.