US 12,368,767 B2
Technologies for accelerated HTTP processing with hardware acceleration
Parthasarathy Sarangam, Portland, OR (US); Manasi Deval, Portland, OR (US); and Gregory Bowers, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 26, 2023, as Appl. No. 18/202,408.
Application 17/889,678 is a division of application No. 16/022,949, filed on Jun. 29, 2018, granted, now 11,451,609, issued on Sep. 20, 2022.
Application 18/202,408 is a continuation of application No. 17/889,678, filed on Aug. 17, 2022, granted, now 11,757,973.
Claims priority of provisional application 62/644,048, filed on Mar. 16, 2018.
Prior Publication US 2023/0421627 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 67/02 (2022.01); H04L 9/40 (2022.01); H04L 69/04 (2022.01); H04L 69/164 (2022.01); H04L 69/166 (2022.01)
CPC H04L 67/02 (2013.01) [H04L 63/0485 (2013.01); H04L 69/04 (2013.01); H04L 69/164 (2013.01); H04L 69/166 (2013.01); H04L 63/0428 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A computing device comprising:
a network interface controller comprising circuitry to:
receive a packet having at least one packet header;
generate a decrypted packet header of the packet header of the packet; and
select a receive queue of multiple receive queues associated with multiple respective processor cores based, at least in part, on Hypertext Transport Protocol (HTTP) action data and/or HTTP object data in the decrypted packet header;
wherein:
the selected receive queue is to be used in association with packet data steering.