US 12,368,413 B2
Circuit and method for biasing a transistor and corresponding device
Herwig Wappis, Villach (AT); Peter Singerl, Villach (AT); Martin Mataln, Rosegg (AT); and Gerhard Maderbacher, Gleisdorf (AT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Feb. 21, 2023, as Appl. No. 18/172,008.
Claims priority of application No. 22159753 (EP), filed on Mar. 2, 2022.
Prior Publication US 2023/0283243 A1, Sep. 7, 2023
Int. Cl. G05F 3/02 (2006.01); G05F 3/20 (2006.01); H03F 1/02 (2006.01); H03F 1/30 (2006.01); H03K 19/0175 (2006.01); H03M 1/06 (2006.01)
CPC H03F 1/302 (2013.01) [G05F 3/205 (2013.01); H03F 1/0266 (2013.01); H03K 19/0175 (2013.01); H03M 1/0604 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A circuit for biasing a transistor, comprising:
an output terminal configured to be coupled to a control terminal of the transistor; and
circuitry configured to selectively:
in a first state, output a control signal having a first voltage level at the output terminal for setting the transistor to a first transistor state, and
in a second state following the first state, output the control signal at the output terminal for setting the transistor to a second transistor state by first outputting the control signal at a second voltage level different from the first voltage level followed by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage levels over time, wherein the circuitry is configured to select a difference between the second voltage level and the third voltage level based on at least one of a time duration of the first state prior to the second state or the first voltage level.