	US 12,367,945 B2
	Memory and memory system with both long and short sub word lines connected to same row
Sang Woo Yoon, Gyeonggi-do (KR); Hoiju Chung, San Jose, CA (US); and Yoonna Oh, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 13, 2023, as Appl. No. 18/109,234.
Claims priority of provisional application 63/427,247, filed on Nov. 22, 2022.
Claims priority of provisional application 63/316,249, filed on Mar. 3, 2022.
Prior Publication US 2023/0282302 A1, Sep. 7, 2023
Int. Cl. G11C 29/52 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01)

CPC G11C 29/52 (2013.01) [G11C 7/1096 (2013.01); G11C 8/08 (2013.01)]

3 Claims

1. A memory comprising:

a plurality of long sub-word lines included in a K^throw, where K is an integer equal to or greater than 0;

a plurality of first memory cells coupled to the long sub-word lines;

a plurality of short sub-word lines included in the K^throw, the number of the short sub-word lines being less than the number of the long sub-word lines;

a plurality of second memory cells coupled to the short sub-word lines; and

a memory error correction code generation circuit configured to generate a memory error correction code based on write data,

wherein when the K^throw is selected during a write operation, a portion of the second memory cells is configured to store therein the memory error correction code and a portion of the second memory cells and a portion of the first memory cells are configured to store therein the write data.