US 12,367,938 B2
Semiconductor memory with different threshold voltages of memory cells
Noboru Shibata, Kawasaki (JP); and Hironori Uchikawa, Fujisawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 4, 2023, as Appl. No. 18/527,941.
Application 18/527,941 is a continuation of application No. 17/735,196, filed on May 3, 2022, granted, now 11,837,294.
Application 17/735,196 is a continuation of application No. 16/832,891, filed on Mar. 27, 2020, granted, now 11,355,202, issued on Jun. 7, 2022.
Application 16/832,891 is a continuation of application No. 16/123,162, filed on Sep. 6, 2018, granted, now 10,607,707, issued on Mar. 31, 2020.
Claims priority of application No. 2018-029437 (JP), filed on Feb. 22, 2018.
Prior Publication US 2024/0185930 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 7/08 (2006.01); G11C 8/14 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/26 (2013.01) [G11C 7/08 (2013.01); G11C 8/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02); G11C 2207/2245 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory comprising:
first to N-th memory cells, N being an integer of 3 or more;
first to N-th bit lines connected to the first to N-th memory cells, respectively;
first to N-th latch circuits connected to the N-th bit lines; and
a controller, wherein
each of threshold voltages of the first to N-th memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, and a fourth threshold voltage higher than the third threshold voltage,
data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell, based on a data allocation,
the controller is configured to perform a read operation for one bit data based on the first to N-th memory cells, respectively,
the controller applies, to read the data of one of the first bit, the second bit, the third bit, the fourth bit, the fifth bit, or the sixth bit, one or more kinds of read voltages to gates of the first to N-th memory cells in the read operation to cause the first to N-th latch circuits to store first to N-th interim data, respectively, and output the read data depending on the data allocation, and
in the data allocation, a combination of the first to N-th memory cell commonly each set with the fourth threshold voltage does not overlap with another combination.