US 12,367,926 B2
Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays
Gururaj K. Shamanna, Austin, TX (US); Naveen Kumar M., Bangalore (IN); Jagadeesh Chandra Salaka, Bangalore (IN); Pascal A. Meinerzhagen, Hillsboro, OR (US); Sravan K. Puchakayala, Folsom, CA (US); and Iqbal Rajwani, Roseville, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 18, 2021, as Appl. No. 17/504,252.
Prior Publication US 2023/0123514 A1, Apr. 20, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a set of sense amplifiers, each sense amplifier to connect to a respective column of memory cells of a memory array; and
a control circuit to assert an enable signal for the set of sense amplifiers on a conductive path which is connected to each of the sense amplifiers, each sense amplifier to sense a memory cell of the respective column of memory cells while the enable signal is asserted, and the control circuit to de-assert the enable signal in response to a feedback signal, wherein a change in a level of the feedback signal indicates that the enable signal has been received at a sense amplifier of the set of sense amplifiers.