US 12,367,924 B2
SRAM design with four-poly-pitch
Chih-Chuan Yang, Hsinchu (TW); Feng-Ming Chang, Hsinchu (TW); Kuo-Hsiu Hsu, Hsinchu (TW); and Ping-Wei Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 14, 2024, as Appl. No. 18/744,280.
Application 18/744,280 is a continuation of application No. 18/306,757, filed on Apr. 25, 2023, granted, now 12,046,276.
Application 18/306,757 is a continuation of application No. 17/528,929, filed on Nov. 17, 2021, granted, now 11,657,869, issued on May 23, 2023.
Application 17/528,929 is a continuation of application No. 16/926,249, filed on Jul. 10, 2020, granted, now 11,205,474, issued on Dec. 21, 2021.
Prior Publication US 2024/0331766 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/412 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/412 (2013.01) [H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a first active structure, a second active structure, and a third active structure, each of the first to third active structures extending along a first lateral direction; and
a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, each of the first to fifth gate structures extending along a second lateral direction perpendicular to the first lateral direction;
wherein the first and second gate structures which are spaced from each other in the first lateral direction are each in parallel with the third gate structure, and the fourth and fifth gate structures which are aligned with each other in the second lateral direction are each in parallel with the third gate structure;
wherein the first to third active structures and the first to fifth gate structures collectively form a memory cell.