| CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 16/04 (2013.01); G11C 2211/4016 (2013.01)] | 9 Claims |
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1. A semiconductor element memory device comprising:
a semiconductor body that stands on a substrate in a vertical direction relative to the substrate or that extends along the substrate in a horizontal direction relative to the substrate;
a first impurity region and a second impurity region that are disposed at respective ends of the semiconductor body;
a gate insulator layer that is in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
a first gate conductor layer that partially or entirely covers the gate insulator layer; and
a second gate conductor layer that is adjacent to the first gate conductor layer and that is in contact with a side surface of the gate insulator layer, wherein
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside the semiconductor body,
in a write operation, a voltage of the semiconductor body is made equal to a first data retention voltage that is higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by at least a built-in voltage, and
in an erase operation, the voltage of the semiconductor body is controlled so as to be higher than the first data retention voltage with first capacitive coupling between the first gate conductor layer and the semiconductor body and second capacitive coupling between the second gate conductor layer and the semiconductor body, and a group of remaining positive holes among the group of positive holes are discharged from inside the semiconductor body through one or both of the first impurity region and the second impurity region until the voltage of the semiconductor body becomes equal to a voltage higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by a voltage close to the built-in voltage, and
the voltage of the semiconductor body is made equal to a second data retention voltage lower than the first data retention voltage with the first capacitive coupling and the second capacitive coupling.
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