| CPC G11C 11/40615 (2013.01) | 20 Claims |
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1. A semiconductor device comprising:
an interval control circuit configured to generate a detection interval signal by detecting that an internal address, which is input right before a pulse of a row hammer command signal is generated, is sampled as a target address;
a signal correction circuit configured to generate a correction random signal to adjust the internal address so that the internal address is sampled as the target address less than or equal to a preset number of times between consecutive pulses of the row hammer command signal during a designation interval and a detection interval in which the detection interval signal is activated; and
a row hammer refresh circuit configured to execute a row hammer refresh based on the target address that is generated in response to the correction random signal.
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