| CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01)] | 15 Claims |
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1. A gate driving circuit, comprising a plurality of cascaded gate driving units, wherein each of the gate driving units comprises:
a pull-up control module, wherein an output terminal of the pull-up control module is connected to a pull-up node, for stepwise increasing a potential of the pull-up node;
an inversion module, wherein an input terminal of the inversion module is connected to the pull-up node, for outputting an anti-leakage control signal in response to an increased potential of the pull-up node; and
a feedback module, wherein a control terminal of the feedback module is connected to an output terminal of the inversion module, one terminal of the feedback module is connected to the pull-up node, and another terminal of the feedback module is connected to a first low potential line, for reducing leakage from the pull-up node to the first low potential line in response to the anti-leakage control signal,
wherein, the pull-up control module includes a pull-up control transistor, wherein one of a source/drain of the pull-up control transistor is connected to a Jth stage scanning line, a gate of the pull-up control transistor is connected to a Jth stage cascade line, and another one of the source/drain of the pull-up control transistor is connected to the pull-up node;
wherein the Jth stage scanning line is configured to transmit a Jth stage scanning signal having a trimmed rising edge, and the Jth stage cascade line is configured to transmit a Jth stage cascade signal having a trimmed rising edge;
wherein each of the gate driving units further includes: a pull-up transistor, wherein one of a source/drain of the pull-up transistor is connected to an Nth stage clock line, a gate of the pull-up transistor is connected to the pull-up node, and another one of the source/drain of the pull-up transistor is connected to an Nth stage scanning line; and a cascade transistor, wherein one of a source/drain of the cascade transistor is connected to the Nth stage clock line, a gate of the cascade transistor is connected to the pull-up node, and another one of the source/drain of the cascade transistor is connected to an Nth stage cascade line;
wherein the Nth stage clock line is configured to transmit an Nth stage clock signal having a trimmed rising edge; the Nth stage scanning line is configured to transmit an Nth stage scanning signal having a trimmed rising edge, a waveform of the Nth stage scanning signal is the same as a waveform of the Jth stage scanning signal and a phase of the Nth stage scanning signal lags behind a phase of the Jth stage scanning signal; a waveform of the Nth stage cascade signal is the same as a waveform of the Jth stage cascade signal, and a phase of the Nth stage cascade signal lags behind a phase of the Jth stage cascade signal; and
wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔;
wherein, the pull-up node is configured to provide a pull-up control signal including at least one step pulse, wherein each step pulse of the at least one step pulse includes a first potential pulse and a second potential pulse in succession, and a potential of the first potential pulse is lower than a potential of the second potential pulse.
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