US 12,367,803 B2
Gamma voltage conversion circuit, display device and gamma voltage conversion method
Shaoru Zhang, Beijing (CN); Mingchun Lai, Beijing (CN); Xin Duan, Beijing (CN); Wei Sun, Beijing (CN); and Shuhuan Yu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/286,617
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jul. 1, 2022, PCT No. PCT/CN2022/103345
§ 371(c)(1), (2) Date Oct. 12, 2023,
PCT Pub. No. WO2023/000956, PCT Pub. Date Jan. 26, 2023.
Claims priority of application No. 202110835123.7 (CN), filed on Jul. 23, 2021.
Prior Publication US 2024/0221588 A1, Jul. 4, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 3/20 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0297 (2013.01); G09G 2320/0276 (2013.01); G09G 2320/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gamma voltage conversion circuit, comprising:
a first voltage divider circuit having a plurality of first input terminals and a plurality of first voltage divider output terminals, wherein each of the plurality of first input terminals is configured to receive a first gamma voltage signal input by a first gamma channel, the first voltage divider circuit is configured to generate a plurality of first analog voltage signals according to the first gamma voltage signal, and each of the plurality of first voltage divider output terminals is configured to output one of the plurality of first analog voltage signals;
a Gray code control circuit configured to generate and output a corresponding Gray code control signal according to a grayscale value to be displayed;
a first encoding circuit configured to generate and output a plurality of second analog voltage signals according to the Gray code control signal and one of the plurality of first analog voltage signals; and
a first output control circuit configured to generate and output an analog grayscale voltage signal according to the plurality of second analog voltage signals;
wherein the first encoding circuit comprises a plurality of switch sub-circuits and a plurality of output sub-circuits; each of the plurality of switch sub-circuits comprises a plurality of branch circuits, each branch circuit has a second input terminal and a plurality of third input terminals, each second input terminal is configured to receive the first analog voltage signal output by one of the first voltage divider output terminals, each of the third input terminals is configured to receive a first preset bit of the Gray code control signal, each branch circuit is configured to control a turn-on or turn-off state of the branch circuit according to a plurality of first preset bits of the Gray code control signal, and generate a voltage signal to be output according to a received first analog voltage signal while the branch circuit is in the turn-on state; and each of the output sub-circuits has a plurality of fourth input terminals and a plurality of fifth input terminals, each of the fourth input terminals is configured to receive the voltage signal to be output from one of the switch sub-circuits, each of the fifth input terminals is configured to receive a second preset bit of the Gray code control signal, each output sub-circuit is configured to control itself to be connected to one of the switch sub-circuits according to a plurality of second preset bits of the Gray code control signal, and generate and output the second analog voltage signals according to the received voltage signal to be output;
wherein the plurality of first analog voltage signals are in one-to-one correspondence with grayscale values, the plurality of first voltage divider output terminals are in one-to-one correspondence with the grayscale values, the plurality of second analog voltage signals are in one-to-one correspondence with the grayscale values, and a total number of the grayscale values is 2m, where m is a positive integer; the plurality of switch sub-circuits comprise a plurality of first switch sub-circuits and a plurality of second switch sub-circuits, each first switch sub-circuit comprises 2n branch circuits, and each second switch sub-circuit comprises 2n branch circuits, where n is a positive integer; and the grayscale values are sorted in ascending order, each adjacent n ones of the first voltage divider output terminals form a group; for N groups of the first voltage divider output terminals of which corresponding grayscale values are smaller than or equal to a preset first threshold, each adjacent two groups of the first voltage divider output terminals are connected to the second input terminals of one of the first switch sub-circuits, where N is a positive integer; for M groups of the first voltage divider output terminals of which corresponding grayscale values are greater than or equal to a preset second threshold, each adjacent two groups of the first voltage divider output terminals are connected to the second input terminals of one of the second switch sub-circuits, and the second threshold is greater than the first threshold, where M is a positive integer; and
wherein the plurality of switch sub-circuits further comprises a third switch sub-circuit and a plurality of fourth switch sub-circuits, the third switch sub-circuit comprises k branch circuits, and each of the plurality of fourth switch sub-circuits comprises n branch circuits, where k=(2m−N*n−M*n)/n, and k is a positive integer; and for multiple groups of the first voltage divider output terminals of which corresponding grayscale values are greater than the first threshold and less than the second threshold, the grayscale values corresponding to each group of the first voltage divider output terminals comprise a first grayscale value that is the minimum and n−1 second grayscale values, and the first voltage divider output terminals corresponding to each adjacent n first grayscale values are sequentially and alternately connected to both n second input terminals of the third switch sub-circuit and second input terminals of one of the fourth switch sub-circuits.