US 12,367,411 B2
Enablement of sampling-optimization for gate-level simulation
Hiroshi Horii, Tokyo (JP); and Ikko Hamamura, Tokyo (JP)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,436.
Prior Publication US 2023/0186129 A1, Jun. 15, 2023
Int. Cl. G06F 30/3308 (2020.01); G06N 10/20 (2022.01); G06N 10/40 (2022.01); G06N 10/70 (2022.01); G06N 10/80 (2022.01)
CPC G06N 10/20 (2022.01) [G06F 30/3308 (2020.01); G06N 10/40 (2022.01); G06N 10/70 (2022.01); G06N 10/80 (2022.01)] 20 Claims
OG exemplary drawing
 
8. A computer-implemented method, comprising:
caching, by a system operatively coupled to a processor, a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset.