US 12,367,331 B2
Approach to child block pinning
Jesse Peter Surprise, Highland, NY (US); Eduard Herkel, New York, NY (US); Ofer Geva, Poughkeepsie, NY (US); and Faisal Hasan, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Feb. 15, 2022, as Appl. No. 17/671,696.
Prior Publication US 2023/0259684 A1, Aug. 17, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/327 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01)] 20 Claims
OG exemplary drawing
 
9. A computer-implemented method of optimizing placement of child-block pins in a parent-level hierarchy, the method comprising:
placing, by a small-block processing module, a plurality of initial child-block pins corresponding to child-level blocks included in the parent-level hierarchy;
placing, by a child processing module, at least one logic element at a location within a given child block among the plurality of child blocks based on the placement of the initial child pins;
discarding, by the child processing module, the plurality of initial child pins while maintaining the location of the at least one logic element;
placing, by the child processing module, at least one optimized child pin based at least in part on the location of the at least one logic element;
performing, by the child processing module, an abstraction operation on the at least one logic element while maintaining the at least one child pin within the child blocks; and
performing, by a hierarchical large block synthesis (hLBS) module, an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.