US 12,367,170 B2
Stream routing and ide enhancements for PCIe
David J. Harriman, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 8, 2021, as Appl. No. 17/225,221.
Claims priority of provisional application 63/126,964, filed on Dec. 17, 2020.
Prior Publication US 2021/0255973 A1, Aug. 19, 2021
Int. Cl. G06F 13/42 (2006.01); G06F 13/20 (2006.01); G06F 13/40 (2006.01); H04L 9/40 (2022.01); H04L 45/745 (2022.01)
CPC G06F 13/4295 (2013.01) [G06F 13/20 (2013.01); G06F 13/4282 (2013.01); H04L 45/745 (2013.01); H04L 63/0457 (2013.01); G06F 2213/0026 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one port to interface with a partner port on another device; and
a router circuit coupled to the at least one port, the router circuit comprising:
a first router to route packets based on address information; and
a second router to route packets based on stream information, the stream information comprising a logical connection between a pair of ports, wherein the stream information includes an unencrypted identifier in a packet prefix in non-FLIT mode and orthogonal header content (OHC) in FLIT mode;
wherein the router circuit is to direct a first packet having first stream information to the second router and the second router is to route the first packet to a target port based at least in part on the stream information, wherein the first packet includes an integrity and data encryption (IDE) packet having an unencrypted portion comprising the stream information and an encrypted portion comprising a header including the address information.