US 12,367,159 B2
Low latency memory access
Frederick A. Ware, Los Altos Hills, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 12, 2023, as Appl. No. 18/133,700.
Application 18/133,700 is a continuation of application No. 17/461,064, filed on Aug. 30, 2021, granted, now 11,657,006.
Application 17/461,064 is a continuation of application No. 16/418,553, filed on May 21, 2019, granted, now 11,132,307, issued on Sep. 28, 2021.
Claims priority of provisional application 62/676,670, filed on May 25, 2018.
Prior Publication US 2023/0297518 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1615 (2013.01) [G06F 13/1689 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory component, comprising:
a memory core;
synchronous control circuitry to, based on the memory component being in a first mode, access the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface; and
asynchronous control circuitry to, based on the memory component being in a second mode, access the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links to communicate data bidirectionally when the memory component is in the first mode.