US 12,367,157 B2
Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices
Adrian Montero, Austin, TX (US); Conrado Blasco, San Mateo, CA (US); Paul Kitchin, Austin, TX (US); and Huzefa Sanjeliwala, Austin, TX (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 4, 2024, as Appl. No. 18/626,506.
Application 18/626,506 is a continuation of application No. 18/168,871, filed on Feb. 14, 2023, granted, now 12,130,751.
Prior Publication US 2024/0273036 A1, Aug. 15, 2024
Int. Cl. G06F 12/1027 (2016.01); G06F 9/455 (2018.01)
CPC G06F 12/1027 (2013.01) [G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor device, comprising:
a translation lookaside buffer (TLB) comprising a plurality of TLB entries;
a TLB metadata buffer comprising a plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; and
a memory management unit (MMU) configured to:
receive a first memory access request comprising a first virtual address (VA); and
responsive to receiving the first memory access request, access a TLB entry for the first VA among the plurality of TLB entries of the TLB, based on an active TLB metadata pointer to a TLB metadata buffer entry among the plurality of TLB metadata buffer entries,
wherein the MMU is further configured to, prior to receiving the first memory access request:
select the TLB metadata buffer entry among the plurality of TLB metadata buffer entries for use in accessing the TLB;
store a pointer to the TLB metadata buffer entry as the active TLB metadata pointer;
receive a second memory access request comprising the first VA; and
responsive to receiving the second memory access request, generate the TLB entry in the TLB for the first VA, the TLB entry comprising a TLB tag that stores the active TLB metadata pointer in lieu of the TLB metadata of the TLB metadata buffer entry.