US 12,367,154 B2
Logging guest physical address for memory access faults
John Ingalls, Sunnyvale, CA (US); and Andrew Waterman, Berkeley, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Dec. 21, 2022, as Appl. No. 18/086,635.
Claims priority of provisional application 63/293,060, filed on Dec. 22, 2021.
Prior Publication US 2023/0195647 A1, Jun. 22, 2023
Int. Cl. G06F 12/1009 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/1027 (2013.01); G06F 2212/1032 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a processor pipeline configured to fetch and execute instructions, including load instructions and store instructions;
a translation lookaside buffer configured to perform two-stage address translation to translate guest virtual addresses to physical addresses, wherein an entry of the translation lookaside buffer includes a tag that includes a guest virtual address and data that includes a physical address;
a data store configured to:
hold a guest physical address and the guest virtual address; and
store a guest fault flag indicating whether a fault condition corresponding to a first guest physical address occurred during a first stage or a second stage of the two-stage address translation; and
a fault handling circuitry that is configured to:
responsive to the fault condition on a hit in the translation lookaside buffer for a first address translation request from the processor pipeline for a first guest virtual address, invoke a single-stage page table walk with the first guest virtual address to obtain the first guest physical address; and
store the first guest physical address with the first guest virtual address in the data store.