US 12,367,153 B2
Multi-level starvation widget
Sankaranarayanan Gurumurthy, Austin, TX (US); and Anil Harwani, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,479.
Prior Publication US 2024/0111684 A1, Apr. 4, 2024
Int. Cl. G06F 12/0897 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 2212/601 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
detecting, by a first control circuit associated with a first level cache within a cache hierarchy of a processor, at least one stalled memory request for the first level cache that includes an outstanding memory request that is waiting on a second level cache within the cache hierarchy that is higher than the first level cache; and
communicating, by the first control circuit to a second control circuit associated with the second level cache, that the first level cache is experiencing a starvation issue due to the outstanding memory request having to wait on the second level cache and to enable the second level cache to perform starvation-remediation actions.