US 12,367,146 B1
Shared memory device with hybrid coherency
David Alan Boles, Austin, TX (US); David Joseph Hawkins, Austin, TX (US); and Sandipkumar Ladhani, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Mar. 14, 2024, as Appl. No. 18/604,816.
Int. Cl. G06F 12/0815 (2016.01); G06F 12/0806 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device including:
a memory array having a first memory region and a second memory region;
a plurality of communication ports configured to couple the memory device to a plurality of host computers of a data processing system and enabling:
a first host computer of the plurality of host computers to:
write a data block to the second memory region;
write a message, including a data descriptor of the data block, to the first or second memory region; and
write message metadata, associated with the message, to the first memory region; and
a second host computer of the plurality of host computers to read the message metadata, the data descriptor and the associated data block; and
coherency control circuitry configured to control coherency of data in the first memory region, including sending an invalidation request to the second host computer to invalidate a copy of the message metadata stored in a local cache of the second host computer, the invalidation request sent in response to the first host computer writing the message metadata to the first memory region.