	US 12,367,133 B2
	Apparatuses and methods for training operations
Osamu Nagashima, Kanagawa (JP); Yoshinori Matsui, Kanagawa (JP); Keun Soo Song, Boise, ID (US); Hiroki Takahashi, Tokyo (JP); and Shunichi Saito, Kanagawa (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 17, 2023, as Appl. No. 18/353,639.
Claims priority of provisional application 63/369,612, filed on Jul. 27, 2022.
Prior Publication US 2024/0078173 A1, Mar. 7, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G11C 11/4076 (2006.01)

CPC G06F 12/023 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G11C 11/4076 (2013.01)]

20 Claims

1. A method comprising:

providing a first active clock signal from a controller to a memory;

providing a command from the controller to the memory to cause the memory to enter a training mode;

providing a second active clock signal from the controller to the memory;

receiving at the controller an output from the memory; and

adjusting a phase relationship between the first active clock signal and the second active clock signal when the output is a first state; or

maintaining the phase relationship between the first active clock signal and the second active clock signal when the output is a second state.