| CPC G06F 11/0751 (2013.01) [G06F 11/073 (2013.01); H04L 1/0061 (2013.01)] | 25 Claims |
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1. An apparatus, comprising:
a memory array;
a delay circuit configured to delay an input signal to obtain a timing signal;
an error detection circuit configured to detect errors in a modified data signal received at the error detection circuit and to output an error signal for the modified data signal;
logic configured to receive and combine the error signal and the modified data signal to obtain a corrected data signal, wherein the timing signal is configured to control a propagation of the error signal to the logic relative to a propagation of the modified data signal to the logic; and
a calibration circuit configured to adjust a delay of the delay circuit based at least in part on a duration for the error detection circuit to output the error signal for the modified data signal, wherein a reception of the error signal and a reception of the modified data signal at the logic is aligned based at least in part on adjusting the delay of the delay circuit, and wherein the calibration circuit is configured to inject an error into a data signal to obtain the modified data signal.
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