US 12,367,063 B2
Technology to measure latency in hardware with fine-grained transactional filtration
Michael Cole, Folsom, CA (US); Pattabhiraman K, Banglore (IN); and Ankita A. Agarwal, Dublin, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 16, 2021, as Appl. No. 17/553,359.
Prior Publication US 2023/0195503 A1, Jun. 22, 2023
Int. Cl. G06F 9/44 (2018.01); G06F 9/46 (2006.01)
CPC G06F 9/466 (2013.01) 24 Claims
OG exemplary drawing
 
1. A computing system comprising:
a network controller; and
a graphics processor coupled to the network controller, the graphics processor including:
a set of configuration registers to maintain state information,
a filter coupled to the set of configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis,
a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis,
a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and
an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.