US 12,367,047 B2
Debug trace circuitry configured to generate a record including an address pair and a counter value
Bruce Ableidinger, Vancouver, WA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Nov. 6, 2023, as Appl. No. 18/502,270.
Claims priority of provisional application 63/432,099, filed on Dec. 13, 2022.
Prior Publication US 2024/0192960 A1, Jun. 13, 2024
Int. Cl. G06F 9/44 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3861 (2013.01) [G06F 9/30058 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a processor pipeline configured to execute instructions;
a debug trace circuitry that is configured to:
responsive to an indication of a non-sequential execution of an instruction by the processor pipeline, generate a record including an address pair and one or more counter values, wherein the address pair includes a first address corresponding to a first instruction before the non-sequential execution and a second address corresponding to a second instruction resulting in the non-sequential execution, and wherein the one or more counter values indicate a count of instructions executed; and
a delta counter configured to generate the one or more counter values and to clear to zero after the record is generated.