US 12,367,044 B2
Tracking instruction handling using opcode matching in processor-based devices
Prasanna Srinivasan, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 25, 2023, as Appl. No. 18/473,414.
Prior Publication US 2025/0103336 A1, Mar. 27, 2025
Int. Cl. G06F 9/30 (2018.01); G06F 11/34 (2006.01); G06F 11/36 (2025.01); G06F 11/362 (2025.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30101 (2013.01); G06F 9/3013 (2013.01); G06F 9/30189 (2013.01); G06F 11/3466 (2013.01); G06F 11/3648 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor device, comprising:
an opcode match register;
an accumulator register; and
an instruction processing circuit configured to:
determine that an instruction of a plurality of instructions matches an opcode value stored in the opcode match register; and
responsive to determining that the instruction matches the opcode value stored in the opcode match register, modify a value stored in the accumulator register without halting or modifying program control flow;
wherein:
the value stored in the accumulator register represents a total time spent processing occurrences of the instruction; and
the instruction processing circuit is configured to modify the value stored in the accumulator register by a time value indicating a time interval between fetching of the instruction and an occurrence of an end event.