US 12,367,025 B2
Compiler, generation method, chip, and execution method
Seiya Tokui, Tokyo (JP)
Assigned to Preferred Networks, Inc., Tokyo (JP)
Filed by Preferred Networks, Inc., Tokyo (JP)
Filed on Oct. 24, 2022, as Appl. No. 18/048,934.
Claims priority of application No. 2021-174381 (JP), filed on Oct. 26, 2021.
Prior Publication US 2023/0129676 A1, Apr. 27, 2023
Int. Cl. G06F 8/51 (2018.01)
CPC G06F 8/51 (2013.01) 20 Claims
OG exemplary drawing
 
1. A compiler for generating a machine code to be executed in a chip including a plurality of distributed memories connected by a tree structure, the compiler comprising:
at least one memory; and
at least one processor,
wherein the at least one processor is configured to:
acquire a tensor to be processed in the chip;
perform an associating process in which each element of the tensor is associated with an address in the plurality of distributed memories included in the chip, based on a stride and a number of divisions in a hierarchy of the tree structure with respect to the tensor,
generate the machine code to be executed in the chip based on the associating process,
wherein the tree structure corresponds to a hardware configuration of the chip, and includes at least a first hierarchy and a second hierarchy, the second hierarchy being higher than the first hierarchy,
wherein the first hierarchy includes a plurality of first blocks, and
wherein the associating process further includes dividing the tensor according to at least a number of divisions in the first hierarchy and specifying to which of the plurality of first blocks in the first hierarchy each element after the division of the tensor belongs according to a stride in the first hierarchy.