US 12,366,975 B2
Automated error correction with memory refresh
Hyun Yoo Lee, Boise, ID (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 20, 2024, as Appl. No. 18/582,356.
Application 18/582,356 is a continuation of application No. 17/460,013, filed on Aug. 27, 2021, granted, now 11,907,544.
Claims priority of provisional application 63/131,749, filed on Dec. 29, 2020.
Claims priority of provisional application 63/072,715, filed on Aug. 31, 2020.
Prior Publication US 2024/0192862 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
at least one memory array comprising multiple memory cells;
at least one buffer memory;
error logic coupled to the at least one memory array and the at least one buffer memory, the error logic configured to:
determine that data includes at least one error, the data corresponding to an address that is associated with the at least one memory array; and
store at least part of the address in the at least one buffer memory based on a determination that the data includes the at least one error; and
refresh control circuitry coupled to the at least one memory array, the refresh control circuitry configured to:
write corrected data at the address that is associated with the at least one memory array in conjunction with a refresh operation that includes the address effective to obviate correction of the at least one error with a separate write operation.