US 12,366,974 B2
Memory system performing multi-step write operation and control method thereof
Yuko Noda, Kawasaki Kanagawa (JP); Kiwamu Watanabe, Kawasaki Kanagawa (JP); Masahiro Saito, Tokyo (JP); and Yoshiki Takai, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 11, 2023, as Appl. No. 18/448,481.
Claims priority of application No. 2022-128848 (JP), filed on Aug. 12, 2022.
Prior Publication US 2024/0053903 A1, Feb. 15, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a non-volatile memory including a plurality of memory cells; and
a controller configured to perform a multi-step write operation to write multi-bit data with respect to each of target memory cells through a first programming to set a first threshold voltage and then a second programming to set a second threshold voltage and manage an order of performing the first programming and the second programming with respect to each of the target memory cells,
wherein the controller is configured to, during the multi-step write operation:
determine a time period elapsed from a first time at which the first programming with respect to a first memory cell of the target memory cells has been performed;
in a case where the second programming is to be performed with respect to the first memory cell according to the order but the time period is less than a first threshold, change the order to perform the first programming with respect to another one of the target memory cells; and
in a case where the second programming is to be performed with respect to the first memory cell according to the order and the time period is greater than the first threshold, perform the second programming with respect to the first memory cell.