CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01)] | 24 Claims |
1. An apparatus comprising:
a memory; and
one or more hardware processors coupled to the memory and coupled to a channel coupled to a solid state storage device, the one or more hardware processors being configured at least to:
transfer one or more traffic items between portions of a single program operation's write data on the channel coupled to the solid state storage device, wherein the one or more traffic items are not part of the single program operation; and
after the transferring of the one or more traffic items, and in response to determining that the single program operation's write data was not programmed within a predetermined amount of time:
transfer all remaining portions of the single program operation's write data without transferring other one or more traffic items.
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