US 12,366,965 B2
Solid state drive with multiplexed internal channel access during program data transfers
David J. Pelster, Longmont, CO (US); Yogesh B. Wakchaure, Folsom, CA (US); Neelesh Vemula, Sunnyvale, CA (US); Aliasgar S. Madraswala, Folsom, CA (US); David B. Carlton, Oakland, CA (US); Donia Sebastian, Fair Oaks, CA (US); Mark Anthony Golez, Folsom, CA (US); and Xin Guo, San Jose, CA (US)
Assigned to SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA (US)
Filed by SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/373,480.
Application 18/373,480 is a continuation of application No. 16/712,647, filed on Dec. 12, 2019, granted, now 11,797,188.
Prior Publication US 2024/0020013 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory; and
one or more hardware processors coupled to the memory and coupled to a channel coupled to a solid state storage device, the one or more hardware processors being configured at least to:
transfer one or more traffic items between portions of a single program operation's write data on the channel coupled to the solid state storage device, wherein the one or more traffic items are not part of the single program operation; and
after the transferring of the one or more traffic items, and in response to determining that the single program operation's write data was not programmed within a predetermined amount of time:
transfer all remaining portions of the single program operation's write data without transferring other one or more traffic items.