US 12,366,963 B2
Method for storing data and parity data in different chip enabled regions, memory storage device and memory control circuit unit
Chih-Kang Yeh, Kinmen County (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Dec. 25, 2022, as Appl. No. 18/088,604.
Claims priority of application No. 111144536 (TW), filed on Nov. 22, 2022.
Prior Publication US 2024/0168641 A1, May 23, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A data storage method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of chip enabled regions, the data storage method comprising:
receiving at least one write command from a host system, wherein the at least one write command instructs to store target data;
encoding the target data to generate parity data;
sending a first write command sequence, wherein the first write command sequence instructs to store the target data in a first physical management unit, and the first physical management unit crosses the chip enabled regions; and
sending a second write command sequence, wherein the second write command sequence instructs to store the parity data in a second physical management unit, the second physical management unit crosses the chip enabled regions, and the first physical management unit is different from the second physical management unit, wherein
the target data comprises first data, the parity data comprises first parity data, and the first parity data is used to protect the first data,
the first parity data is generated based on encoding of the first data sequentially stored in a default number of the chip enabled regions, the first data and the first parity data can fulfill one physical management unit crossing the chip enabled regions,
the first physical management unit storing the first data in a plurality of first chip enabled regions among the chip enabled regions, and the second physical management unit storing the first parity data in a second chip enabled region among the chip enabled regions different from the first chip enabled regions do not belong to any of one single physical management unit, continuous physical management units, and neighboring physical management units.