US 12,366,959 B2
Data compression for mapping tables
Deping He, Boise, ID (US); and Wenjun Wu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 19, 2024, as Appl. No. 18/610,028.
Claims priority of provisional application 63/459,365, filed on Apr. 14, 2023.
Prior Publication US 2024/0345727 A1, Oct. 17, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory system comprising a volatile memory and a non-volatile memory; and
a controller coupled with the memory system, wherein the controller is configured to cause the apparatus to:
receive, by the memory system, a write command comprising data and a set of logical block addresses associated with the data;
store, to the volatile memory based at least in part on a first set of physical block addresses and a second set of physical block addresses of the non-volatile memory for writing the data, a first mapping between a first logical block address of the set of logical block addresses and the first set of physical block addresses and a second mapping between a second logical block address of the set of logical block addresses and the second set of physical block addresses; and
write the data to the first set of physical block addresses and the second set of physical block addresses based at least in part on storing the first mapping and the second mapping to the volatile memory.