US 12,366,911 B2
Methods and apparatus for selectively extracting and loading register states
Shiva Rao, Belmont, CA (US); and David Munday, Santa Cruz, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 14, 2023, as Appl. No. 18/449,479.
Application 17/686,174 is a division of application No. 16/921,633, filed on Jul. 6, 2020, granted, now 11,287,870, issued on Mar. 29, 2022.
Application 16/258,931 is a division of application No. 15/197,448, filed on Jun. 29, 2016, granted, now 10,216,254, issued on Feb. 26, 2019.
Application 18/449,479 is a continuation of application No. 17/686,174, filed on Mar. 3, 2022, granted, now 11,726,545.
Application 16/921,633 is a continuation of application No. 16/258,931, filed on Jan. 28, 2019, granted, now 10,725,528, issued on Jul. 28, 2020.
Prior Publication US 2024/0012466 A1, Jan. 11, 2024
Int. Cl. G06F 1/32 (2019.01); G01R 31/3177 (2006.01); G06F 1/3234 (2019.01); G06F 9/30 (2018.01); G06F 30/3312 (2020.01)
CPC G06F 1/3278 (2013.01) [G01R 31/3177 (2013.01); G06F 9/30101 (2013.01); G06F 9/3012 (2013.01); G06F 9/30141 (2013.01); G06F 30/3312 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
running an application using registers stored in a first programmable logic device, wherein the registers comprise configuration registers that store a design of the first programmable logic device and user data registers used in the application; and
migrating a function performed by the application by conveying at least some of the configuration registers and at least some of the user data registers from the first programmable logic device to a second programmable logic device.