US 12,366,910 B2
Multi-level loops for computer processor control
Doron Rajwan, Rishon le-Zion (IL); Efraim Rotem, Haifa (IL); Eliezer Weissmann, Haifa (IL); Avinash N. Ananthakrishnan, Portland, OR (US); and Dorit Shapira, Atlit (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 21, 2022, as Appl. No. 18/048,593.
Application 18/048,593 is a continuation of application No. 16/880,167, filed on May 21, 2020, granted, now 11,481,013, issued on Oct. 25, 2022.
Application 16/880,167 is a continuation of application No. 16/252,012, filed on Jan. 18, 2019, granted, now 10,678,319, issued on Jun. 9, 2020.
Application 16/252,012 is a continuation of application No. 15/281,651, filed on Sep. 30, 2016, granted, now 10,216,246, issued on Feb. 26, 2019.
Prior Publication US 2023/0063955 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3228 (2019.01); G06F 1/3203 (2019.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01); G06F 1/3293 (2019.01); G06F 30/34 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01)
CPC G06F 1/3228 (2013.01) [G06F 1/3203 (2013.01); G06F 1/3237 (2013.01); G06F 1/324 (2013.01); G06F 1/3234 (2013.01); G06F 1/3243 (2013.01); G06F 1/3293 (2013.01); G06F 30/34 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01)] 16 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of processing engines; and
control circuitry to:
concurrently execute a first control loop and a second control loop, each iteration of the first control loop to complete in a first time period, and each iteration of the second control loop to complete in a second time period that is shorter than the first time period;
determine, based on a first event detected by the first control loop, a first control action for a first processing engine included in the processor, wherein the first control loop is to monitor a first characteristic of the first processing engine;
determine, based on a second event detected by the second control loop, a second control action for the first processing engine included in the processor, wherein the second control loop is to monitor a second characteristic for the processor as a whole;
select, based on a comparison of the first control action and the second control action, one of the first control action and the second control action as a selected control action; and
subsequent to the comparison, apply the selected control action to the first processing engine included in the processor.