CPC G06F 1/28 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/30072 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3013 (2013.01); G06F 9/3887 (2013.01); G06F 13/26 (2013.01); G06F 9/3004 (2013.01); G06F 9/30105 (2013.01); G06F 9/3016 (2013.01); Y02D 10/00 (2018.01)] | 19 Claims |
1. A device comprising:
a memory;
a register;
a data path including a set of lanes; and
a processor configured to execute a program to:
write data to a field of the register, the data specifying that at least one lane of the set of lanes is powered on;
execute an instruction on the at least one lane of the set of lanes that is powered on;
receive an interrupt;
based on the interrupt, copy the data from the register to the memory;
service the interrupt; and
based on completion of the service of the interrupt, copy the data from the memory to the register.
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