US 12,366,906 B2
Controlling the number of powered vector lanes via a register field
Timothy David Anderson, University Park, TX (US); and Duc Quang Bui, Grand Prairie, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 4, 2024, as Appl. No. 18/627,428.
Application 18/627,428 is a continuation of application No. 17/838,368, filed on Jun. 13, 2022, granted, now 11,989,072.
Application 17/838,368 is a continuation of application No. 16/983,451, filed on Aug. 3, 2020, granted, now 11,360,536, issued on Jun. 14, 2022.
Application 16/983,451 is a continuation of application No. 15/638,407, filed on Jun. 30, 2017, granted, now 10,732,689, issued on Aug. 4, 2020.
Application 15/638,407 is a continuation in part of application No. 14/326,928, filed on Jul. 9, 2014, granted, now 10,175,981, issued on Jan. 8, 2019.
Claims priority of provisional application 61/844,124, filed on Jul. 9, 2013.
Prior Publication US 2024/0248521 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 1/28 (2006.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 13/26 (2006.01)
CPC G06F 1/28 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/30072 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3013 (2013.01); G06F 9/3887 (2013.01); G06F 13/26 (2013.01); G06F 9/3004 (2013.01); G06F 9/30105 (2013.01); G06F 9/3016 (2013.01); Y02D 10/00 (2018.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
a memory;
a register;
a data path including a set of lanes; and
a processor configured to execute a program to:
write data to a field of the register, the data specifying that at least one lane of the set of lanes is powered on;
execute an instruction on the at least one lane of the set of lanes that is powered on;
receive an interrupt;
based on the interrupt, copy the data from the register to the memory;
service the interrupt; and
based on completion of the service of the interrupt, copy the data from the memory to the register.