	US 12,366,606 B2
	Self-functional detection system for tap controller and method thereof
Xue-Shan Han, Shanghai (CN); Xiao-Xiao Mao, Shanghai (CN); and Jin-Dong Zhao, Shanghai (CN)
Assigned to SQ Technology (Shanghai) Corporation, Shanghai (CN); and Inventec Corporation, Taipei (TW)
Filed by SQ Technology (Shanghai) Corporation, Shanghai (CN); and Inventec Corporation, Taipei (TW)
Filed on Feb. 29, 2024, as Appl. No. 18/592,287.
Claims priority of application No. 202311676779.4 (CN), filed on Dec. 7, 2023.
Prior Publication US 2025/0189582 A1, Jun. 12, 2025
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01)

CPC G01R 31/318597 (2013.01) [G01R 31/31724 (2013.01)]

8 Claims

5. A self-functional detection method for TAP controller, comprising:

providing a TAP controller, wherein the TAP controller comprises an uplink circuit, a data transmission hub circuit, a TAP power module, a protocol conversion and data buffer circuit, a power output circuit, a TAP data bus circuit, a TAP IO buffer circuit, a TAP JTAG driver circuit, a discontinuous conduction mode circuit and the at least one communication port;

electrically connecting the data transmission hub circuit to the uplink circuit;

electrically connecting the TAP power module to the uplink circuit;

electrically connecting the protocol conversion and data buffer circuit to the data transmission hub circuit;

electrically connecting the power output circuit to the protocol conversion and data buffer circuit;

electrically connecting the TAP data bus circuit to the protocol conversion and data buffer circuit;

electrically connecting the TAP IO buffer circuit to the protocol conversion and data buffer circuit;

electrically connecting the TAP JTAG driver circuit to the protocol conversion and data buffer circuit;

electrically connecting the discontinuous conduction mode circuit to the data transmission hub circuit, the power output circuit, the data bus circuit, the IO buffer circuit and the JTAG driver circuit;

obtaining a voltage signal, a GPIO signal and a high-speed signal from the power output circuit, the data bus circuit, the IO buffer circuit and the JTAG driver circuit, or obtaining a JTAG signal from the JTAG driver circuit, by the discontinuous conduction mode circuit;

electrically connecting at least one communication port to the power output circuit, the data bus circuit, the IO buffer circuit and the JTAG driver circuit;

providing an external function detection module device, wherein the external function detection module device includes at least one external communication port, a switch circuit, an external power supply module, an external data bus circuit, an ADC and IO buffer circuit, a JTAG signal circuit, a level shift circuit, and a complex programmable logic device;

electrically connecting the at least one external communication port to the at least one communication port;

electrically connecting the switch circuit to the external communication port, and selecting the at least one communication port electrically connected to the at least one external communication port, by the switch circuit;

electrically connecting the external power supply module to the switch circuit;

electrically connecting the external data bus circuit to the external communication port;

electrically connecting the ADC and IO buffer circuit to the external communication port;

electrically connecting the JTAG signal circuit to the external communication port;

electrically connecting the level shift circuit to the JTAG signal circuit;

electrically connecting the CPLD to the external data bus circuit, the ADC and IO buffer circuit and the level shift circuit; and

electrically connecting the data device to the TAP controller, and obtaining the voltage signal, the GPIO signal and the high-speed signal from the DCM circuit through an API and displaying the voltage signal, the GPIO signal and the high-speed signal, or obtaining the JTAG signal from the DCM circuit through the API and displaying the JTAG signal, by the data device.