| CPC G01R 31/2836 (2013.01) | 20 Claims |

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1. A semiconductor device comprising:
a first crack detection circuit configured to receive a first external detection signal and output the first external detection signal as a first internal detection signal through a first metal line or configured to receive the first internal detection signal through the first metal line and output the first internal detection signal as the first external detection signal; and
a second crack detection circuit configured to receive the first internal detection signal and output the first internal detection signal as a second internal detection signal through a second metal line or configured to receive the second internal detection signal through the second metal line and output the second internal detection signal as the first internal detection signal,
wherein the second crack detection circuit is configured to set a logic level of one of the first internal detection signal and the second internal detection signal based on one of a first high setting signal and a first low setting signal.
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