US 12,040,289 B2
Interposer including a copper edge seal ring structure and methods of forming the same
Hong-Seng Shue, Hsinchu (TW); Ming-Da Cheng, Taoyuan (TW); Ching-Wen Hsiao, Hsinchu (TW); Yao-Chun Chuang, Hsinchu (TW); Yu-Tse Su, Chiayi (TW); and Chen-Shien Chen, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 26, 2021, as Appl. No. 17/412,530.
Prior Publication US 2023/0065794 A1, Mar. 2, 2023
Int. Cl. H01L 23/58 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bonded assembly comprising and interposer and at least one semiconductor die, wherein the interposer comprises:
interconnect-level dielectric material layers embedding redistribution interconnect structures, wherein the interconnect-level dielectric material layers comprise organic polymer materials;
package-side bump structures embedded in a package-side dielectric material layer that is located on a first side of the interconnect-level dielectric material layers, wherein the package-side dielectric material layer comprises a package-side silicon nitride layer, and is in direct contact with a bottommost organic polymer material among the organic polymer materials, wherein bonding surfaces of the package-side bump structures are located within a first horizontal plane within which an entirety of a horizontal surface of the package-side dielectric material layer is located;
at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers;
a bonding-level dielectric layer located on the at least one dielectric capping layer;
metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, wherein distal planar surfaces of the metallic pad structures that are most distal from the first horizontal plane are located within a second horizontal plane;
die-side bump structures located on the distal planar surfaces of the metallic pad structures; and
an edge seal ring structure vertically extending from the first horizontal plane to the second horizontal plane and comprising a vertical stack of metallic ring structures that are free of aluminum and laterally surrounding the package-side bump structures and each of the redistribution interconnect structures, wherein the vertical stack of metallic ring structures comprises a package-side metallic ring structure that is embedded within the package-side dielectric material layer such that inner sidewalls of the package-side metallic ring structure contact an inner portion of the package-side dielectric material layer that is laterally surrounded by the package-side metallic ring structure, and outer sidewalls of the package-side metallic ring structure contact an outer portion of the package-side dielectric material layer that laterally surrounds the package-side metallic ring structure,
and wherein the bonded assembly further comprises:
first solder material portions bonded to the package-side bump structures of the interposer;
a first underfill material portion in direct contact with the first solder material portions, in direct contact with the horizontal surface of the package-side dielectric material layer, and in direct contact with a bottom surface of a bottommost metallic ring structure within the vertical stack of metallic ring structures within the first horizontal plane, the bottom surface of the bottommost metallic ring structure not being in direct contact with any solder material; and
second solder material portions bonded to the die-side bump structures and the at least one semiconductor die and located on an opposite side of the first solder material portions.