CPC H01L 23/5389 (2013.01) [H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01)] | 20 Claims |
1. A method, comprising:
placing first semiconductor dies to a semiconductor wafer comprising second semiconductor dies, the semiconductor wafer comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate;
forming grooves on the semiconductor wafer, the grooves extending through the interconnect structure, and the semiconductor substrate being revealed by the grooves;
forming an insulating encapsulation over the semiconductor wafer to laterally encapsulate the first semiconductor dies and fill the grooves; and
performing a wafer sawing process to saw the insulating encapsulation and the semiconductor wafer along the grooves, wherein a portion of the insulating encapsulation remains on sidewalls of the interconnect structure after performing the wafer sawing process.
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