| CPC H01L 23/53295 (2013.01) [H01L 21/7682 (2013.01); H01L 23/5226 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a multilayer dielectric layer having a lower layer, a middle layer, and an upper layer, wherein a composition of the middle layer is different than a composition of the upper layer and a composition of the lower layer;
a gate structure disposed in the lower layer, the middle layer, and the upper layer of the multilayer dielectric layer, wherein the gate structure is disposed between a first epitaxial source/drain and a second epitaxial source/drain along a first direction, the multilayer dielectric layer is disposed over the first epitaxial source/drain and the second epitaxial source/drain, the gate structure extends lengthwise along a second direction, and the second direction is different than the first direction;
a source/drain interconnect disposed in the lower layer, the middle layer, and the upper layer of the multilayer dielectric layer, wherein the source/drain interconnect includes a source/drain contact and a source/drain via, the source/drain interconnect connects the first epitaxial source/drain to a conductive line, the source/drain contact is disposed on the first epitaxial source/drain, the source/drain via is disposed on the source/drain contact, and the source/drain via is disposed between the source/drain contact and the conductive line; and
wherein:
in a first cross-sectional view along the first direction, the source/drain interconnect is disposed between a first gate spacer and a second gate spacer, and
in a second cross-sectional view along the second direction, the source/drain interconnect is disposed between a first portion of the multilayer dielectric layer and a second portion of the multilayer dielectric layer.
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