| CPC G11C 13/0069 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01)] | 20 Claims |
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16. A circuit comprising:
a bit line;
a source line;
a word line;
a memory array comprising a memory cell, the memory cell coupled to the bit line, the source line, and the word line, the memory cell comprising a memory element; and
a bit line driver coupled to the bit line;
a source line driver coupled to the source line; and
a word line driver coupled to the word line,
wherein the bit line driver, the source line driver, and the word line driver are configured program the memory element with a first current during a first period of time and a second current, different than the first current, during a second period of time.
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