US 12,364,103 B2
Display device
Lien-Hsiang Chen, Miao-Li County (TW); Kung-Chen Kuo, Miao-Li County (TW); Sheng-Kai Hsu, Miao-Li County (TW); Hsia-Ching Chu, Miao-Li County (TW); and Mei-Chun Shih, Miao-Li County (TW)
Assigned to Red Oak Innovations Limited, Dublin (IE)
Filed by Red Oak Innovations Limited, Dublin (IE)
Filed on May 9, 2024, as Appl. No. 18/659,476.
Application 18/659,476 is a continuation of application No. 18/209,537, filed on Jun. 14, 2023, granted, now 12,010,881.
Application 18/209,537 is a continuation of application No. 17/719,310, filed on Apr. 12, 2022, granted, now 11,723,239, issued on Aug. 8, 2023.
Application 17/719,310 is a continuation of application No. 16/995,867, filed on Aug. 18, 2020, granted, now 11,335,751, issued on May 17, 2022.
Application 16/995,867 is a continuation of application No. 16/264,761, filed on Feb. 1, 2019, granted, now 10,790,343, issued on Sep. 29, 2020.
Application 16/264,761 is a continuation of application No. 15/695,051, filed on Sep. 5, 2017, granted, now 10,236,329, issued on Mar. 19, 2019.
Claims priority of application No. 201610809206.8 (CN), filed on Sep. 8, 2016.
Prior Publication US 2024/0292679 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10K 50/80 (2023.01); H10K 59/122 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/121 (2023.02) [H10D 30/6739 (2025.01); H10K 50/80 (2023.02); H10K 59/122 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate;
a first transistor and a second transistor disposed on the substrate;
an insulating layer disposed on the first transistor and the second transistor;
a first electrode and a second electrode disposed on the insulating layer, wherein the first electrode is electrically connected to the first transistor through a first via hole passing through the insulating layer, and the second electrode is electrically connected to the second transistor through a second via hole passing through the insulating layer;
a first signal line disposed on the substrate and overlapped with the first electrode and the second electrode; and
a second signal line disposed on the substrate and adjacent to the first signal line, wherein the first signal line and the second signal line extend along a first direction and are separated from each other,
wherein a distance between the first via hole and the second via hole along the first direction is greater than a distance between the first signal line and the second signal line along a second direction different the first direction.