US 12,364,048 B2
Conductive contact for ion through-substrate via
Min-Ying Tsai, Kaohsiung (TW); Cheng-Ta Wu, Shueishang Township (TW); and Yeur-Luen Tu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 1, 2024, as Appl. No. 18/429,535.
Application 17/842,138 is a division of application No. 16/724,744, filed on Dec. 23, 2019, granted, now 11,398,516, issued on Jul. 26, 2022.
Application 18/429,535 is a continuation of application No. 17/842,138, filed on Jun. 16, 2022, granted, now 11,929,379.
Claims priority of provisional application 62/893,333, filed on Aug. 29, 2019.
Prior Publication US 2024/0170524 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/48 (2006.01); H10F 39/00 (2025.01)
CPC H10F 39/809 (2025.01) [H01L 21/7684 (2013.01); H01L 23/481 (2013.01); H10F 39/018 (2025.01); H10F 39/811 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first substrate comprising a front-side and a back-side opposite the front-side;
a first doped region in the first substrate and extending continuously from the front-side to the back-side;
a conductive contact over the first doped region; and
a conductive layer between the first doped region and the conductive contact, wherein the first doped region abuts a lower surface and sides of the conductive layer.