US 12,364,047 B2
Image sensor and method of manufacturing the same
Doowon Kwon, Seongnam-si (KR); Changrok Moon, Seoul (KR); and Kyungtae Lim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 15, 2022, as Appl. No. 17/721,914.
Claims priority of application No. 10-2021-0072068 (KR), filed on Jun. 3, 2021.
Prior Publication US 2022/0392941 A1, Dec. 8, 2022
Int. Cl. H04N 25/79 (2023.01); H01L 23/00 (2006.01); H10F 39/00 (2025.01); H04N 25/78 (2023.01)
CPC H10F 39/809 (2025.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H04N 25/79 (2023.01); H10F 39/018 (2025.01); H10F 39/811 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H04N 25/78 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a first layer comprising a first semiconductor substrate comprising a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate;
a second layer comprising a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction;
a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer;
a third layer comprising a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction; and
a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.