US 12,364,037 B2
Semiconductor device and manufacturing method thereof
Yoshiyuki Kurokawa, Sagamihara (JP); Takayuki Ikeda, Atsugi (JP); Hikaru Tamura, Zama (JP); Munehiro Kozuma, Isehara (JP); Masataka Ikeda, Atsugi (JP); and Takeshi Aoki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jul. 13, 2023, as Appl. No. 18/221,552.
Application 18/221,552 is a continuation of application No. 17/490,009, filed on Sep. 30, 2021, granted, now 11,710,751.
Application 17/490,009 is a continuation of application No. 16/591,983, filed on Oct. 3, 2019, granted, now 11,139,327, issued on Oct. 5, 2020.
Application 16/591,983 is a continuation of application No. 15/177,460, filed on Jun. 9, 2016, granted, now 10,535,691, issued on Jan. 14, 2020.
Application 15/177,460 is a continuation of application No. 14/986,119, filed on Dec. 31, 2015, granted, now 9,515,107, issued on Dec. 6, 2016.
Application 14/986,119 is a continuation of application No. 14/827,809, filed on Aug. 17, 2015, granted, now 9,257,567, issued on Feb. 9, 2016.
Application 14/827,809 is a continuation of application No. 14/600,279, filed on Jan. 20, 2015, granted, now 9,153,619, issued on Oct. 6, 2015.
Application 14/600,279 is a continuation of application No. 13/942,428, filed on Jul. 15, 2013, granted, now 8,964,085, issued on Feb. 24, 2015.
Application 13/942,428 is a continuation of application No. 13/037,889, filed on Mar. 1, 2011, granted, now 8,654,231, issued on Feb. 18, 2014.
Claims priority of application No. 2010-050486 (JP), filed on Mar. 8, 2010.
Prior Publication US 2023/0352502 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10F 39/00 (2025.01); H04N 25/76 (2023.01); H10D 30/67 (2025.01); H10F 30/223 (2025.01); H10F 39/18 (2025.01)
CPC H10F 39/80377 (2025.01) [H04N 25/76 (2023.01); H10D 30/6755 (2025.01); H10F 30/2235 (2025.01); H10F 39/18 (2025.01); H10F 39/802 (2025.01); H10F 39/811 (2025.01); H10F 39/026 (2025.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first pixel in a first row comprising:
a first transistor; and
a first photosensor electrically connected to the first transistor; and
a second pixel in a second row comprising:
a second transistor; and
a second photosensor electrically connected to the second transistor,
wherein a channel formation region of the first transistor and a channel formation region of the second transistor each comprises an oxide semiconductor,
wherein off-state current per micrometer in a channel width of the first transistor is less than or equal to 1×10−17 A/μm, and
wherein a charge accumulation operation is performed in the first pixel and the second pixel at the same time.